Designing integrated circuit (IC) devices such as microprocessors, memory devices, logic devices, radio frequency identification (RFID) tags, etc. can be performed though the use of computer aided design (CAD) software tools. CAD tools and other electronic design automation (EDA) tools are used for all stages of integrated circuit design, from production of the initial circuit design schematic, to electrical simulation of the circuit design to verify proper functionality, conversion of the circuit schematic into a three dimensional physical translation or graphical representation of the schematic devices, verification that the physical device translation is analogous to the circuit design and will provide a functioning device, failure analysis, and optimization of circuit and physical designs to ensure device reliability, stability, and manufacturability.
Design and viewing tools from several different vendors are currently used in the semiconductor industry, including Cadence® (Cadence Design Systems. Inc., San Jose, Calif.), Knights Camelot™ (Magma® Design Automation, San Jose, Calif.), and Spice (SiSoft, Maynard, Mass.), as well as many other design and viewing environments.
The quantity of data required to provide electrical and graphical representation information for each integrated circuit device has increased exponentially as devices have become more complex. A database for each IC device design requires several types of data, each of which contributes to a varying degree to the size of the database.
For example, each device database requires a schematic, which is a symbolic representation of each circuit element (transistors, resistors, capacitors, etc.) of an electrical circuit.
Additionally, each design device database requires a netlist (“logical schematic”) or some other system of storing the schematic connectivity information that can be related to a layout. A netlist is a text list of electrical signals which pertain to the electrical design schematic and to all of the circuit elements which are connected to each signal in the design. The netlist, for example, correlates the leads of the electrical design schematic to the leads depicted in the layout (discussed below). The netlist data can be stored in a verilog file and is used during translation of the schematic data into the layout using a place-and-route tool.
Each device database also requires active trace data, which is a three dimensional physical translation or graphical representation of the active electrical devices from the schematic into a physical depiction of each element of the circuit. The various circuit elements are depicted using a large number of polygon shapes. The active trace data, for example, will depict polysilicon gates, metal lines, implanted semiconductor regions, conductive leads, etc. which form each circuit element of the schematic. This data can be stored in a .gds file (“Graphic Design System” file, a file having a “.gds” extension), in a file having a “.laff” or “.oasis” extension, or in one or more files having some other extension depending on the EDA vendor. Various electrical points of the active trace data are cross referenced to the schematic by the listings in the netlist.
Additionally, each device database requires graphical data pertaining to inactive (“dummy fill”) features, which are typically conductive features which are not active electrically in the circuit but which are used to improve IC device manufacturability. They must be included in the database information so that the positions of functional (active trace) features relative to the positions of the dummy features can be considered to prevent shorts and other interference. As with the functional features, the dummy fill features are represented by polygons. Many of these dummy fill features are complete and identical, and therefore one single polygon instance can be used to define all of the complete dummy fill polygons. However, during production of the layout, an active feature can intersect one of these inactive dummy features. Because the dummy fill features are conductive, they can cause an electrical short or other interference with active features. To prevent interference, the dummy feature shape must be truncated to maintain a specified minimum distance or “critical dimension” between the active feature and the dummy feature. Truncation results in a polygon which does not have the complete polygon shape, thus a separate polygon instance of each different truncated dummy fill polygon must be stored, which further increases the size of the database. Dummy fill data can be stored in files having extensions similar to the active trace data files.
Because active trace data and dummy fill data are often incorporated into the same file, the term “layout data” as used herein may include both functional feature (active trace) data and inactive feature (dummy fill) data unless otherwise noted.
With increasing device complexity, database sizes for cutting edge designs continue to increase at a rate faster than the development of hardware which is able to quickly manage the data. Layout data excluding dummy fill and electrical data can currently approach and exceed 50 gigabytes (GB), requiring several hours to load into memory of a viewer in order to display. Engineers and technicians must load this data to review design and electrical data pertaining to operation of the IC design, correct errors, alter the layout to optimize electrical performance and manufacturability, etc. All active trace, dummy fill, and electrical data must be loaded by a computer each time the device is to be reviewed or modified to determine whether modifications will affect upstream and downstream circuits and structures, and structures on different physical levels either above or below the modified structure. Loading all the layout and electrical data is necessary so that device performance can be monitored as the circuits or structures are modified to ensure a functional and reliable IC device.
Loading the large amount of data in device design databases into a viewer can require several hours, and frequent hardware upgrades are needed to improve data handling performance. Both the long load times and frequent hardware upgrades add to the cost of device production.
A method which improves semiconductor device design data handling to reduce the time required to load the data into viewer memory in order to display would decrease costs by extending the useful lifetime of hardware and would therefore be desirable.